1. Field of the Invention
The invention relates to monitoring circuits and more particularly to monitoring circuits for determining the operational status of a digital system by checking bit patterns generated by the system to determine that they are valid, in the proper sequence, that the total number of valid patterns generated during each operating cycle is as expected, and that the monitored patterns contain no unexpected transitions.
2. Description of the Prior Art
Prior art monitors for monitoring digital systems have typically utilized an address generator to generate addresses to read digital patterns from a memory. The bit patterns being monitored were then compared to the bit patterns read from the memory on a bit by bit basis to determine if the pattern being monitored was as expected. Each time a valid pattern was detected, a counter was stepped one count. At the end of the cycle of the circuit being monitored, the counter was interrogated to determine if the expected number of valid patterns had been detected. If the expected number of valid patterns was not detected, a signal indicating a system malfunction was generated. These monitors also could include transition counters for counting the transitions of signals during a specified time period to determine if the expected number of transitions occurred.
While these systems operated as expected, the address generator required considerable circuit complexity and the transition counter circuit might miss errors due to a misalignment of the transitions with respect to time but not with respect to their number.